Ultra-Low-Power and Ultra-Low-Cost Short-Range Wireless Receivers in Nanoscale CMOS by Zhicheng Lin Pui-In Mak (Elvis) & Rui Paulo Martins

Author:Zhicheng Lin, Pui-In Mak (Elvis) & Rui Paulo Martins
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

For testing under an external LOext source at 4.8 GHz, another set of D1 and D2 is adopted. The output of these two sets of clocks are combined by transmission gates and then selected. Although their transistor sizes can be reduced aggressively to save power, their drivability and robustness in process corners can be degraded. From simulations, the sizing can be properly optimized. The four buffers (Buf1–4) serve to reshape the pulses from DIV2 and enhance the drivability. The timing diagram is shown in Fig. 3.13b. Due to the very small IBIAS for the I/Q-DBMs, a LO amplitude of around 0.4 Vpp is found to be more optimized in terms of NF and gain as simulated and shown in Fig. 3.14a. To gain benefits from it CLO is added to realize a capacitor divider with CMIX,in (input capacitance of the mixer) as shown in Fig. 3.14b. This act brings down the equivalent load (CL,eq) of Buf1–4 by ~33 %.

Fig. 3.14 a Post-layout simulation of NF and gain versus LO’s amplitude, and b additional CLO generates the optimum LO’s amplitude

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